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ATmega128
Table 21. W DT Configuration as a Function of the Fuse Settings of M103C and W DTO N.
How to
Safety
WDT Initial
How to Disable
Change
M103C
Unprogrammed
WDTON
Unprogrammed
Level
1
State
Disabled
the WDT
Timed
Time-out
Timed
sequence
sequence
Unprogrammed
Programmed
2
Enabled
Always enabled
Timed
sequence
Programmed
Unprogrammed
0
Disabled
Timed
No
sequence
restriction
Programmed
Programmed
2
Enabled
Always enabled
Timed
sequence
Figure 28. W atchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer
Control Register –
Bit
7
6
5
4
3
2
1
0
WDTCR
Read/ W rite
Initial Value
–
R
0
–
R
0
–
R
0
WDCE
R/ W
0
WDE
R/ W
0
WDP2
R/ W
0
WDP1
R/ W
0
WDP0
R/ W
0
WDTCR
? Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
? Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the W DE bit is written to logic zero. Otherwise, the W atchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the W DE bit for a W atchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits. See “Timed Sequences for Changing the
Configuration of the W atchdog Timer” on page 57.
? Bit 3 – WDE: Watchdog Enable
W hen the W DE is written to logic one, the W atchdog Timer is enabled, and if the W DE is written
to logic zero, the W atchdog Timer function is disabled. W DE can only be cleared if the W DCE bit
has logic level one. To disable an enabled W atchdog Timer, the following procedure must be
followed:
55
2467X–AVR–06/11
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